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gnucap:manual:tech:modelgen-verilog [2025/05/03 09:35]
felixs duplicate tech:modelgen, with few edits
gnucap:manual:tech:modelgen-verilog [2025/05/19 06:30] (current)
felixs remove TODO tag x3 (done)
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 ===== compiled paramset ===== ===== compiled paramset =====
-TODO: move to tech:modelgen 
  
 The motivation for compiled paramsets, as opposed to interpreted ones, or legacy spice .model instances is speed. Compiled paramsets can be an order of magnitude lighter due to the obvious constant pruning and structural collapse. According to the LRM, Section 6.4.2, paramset identifiers need not be unique, and offer The motivation for compiled paramsets, as opposed to interpreted ones, or legacy spice .model instances is speed. Compiled paramsets can be an order of magnitude lighter due to the obvious constant pruning and structural collapse. According to the LRM, Section 6.4.2, paramset identifiers need not be unique, and offer
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 ===== Partial specialisation ===== ===== Partial specialisation =====
-TODO: move to tech:modelgen 
  
 Given a module declaration, the standard does not offer a way to fix a subset of its parameters, while transparently passing through the others. Paramset sort of does it, but not without changing the behaviour of the specialised device relative to the generic one. Typical use cases are devices specialised without noise, without initial conditions, without additional resistors, without temperature, or with their levels fixed. Given a module declaration, the standard does not offer a way to fix a subset of its parameters, while transparently passing through the others. Paramset sort of does it, but not without changing the behaviour of the specialised device relative to the generic one. Typical use cases are devices specialised without noise, without initial conditions, without additional resistors, without temperature, or with their levels fixed.
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 Another issue is the lack of a portlist in a paramset declaration, allowing for re-using a prototype with its ports renamed. A singleton subcircuit (possibly combined with a paramset) may serve as a workaround, and hence this is low priority. Another issue is the lack of a portlist in a paramset declaration, allowing for re-using a prototype with its ports renamed. A singleton subcircuit (possibly combined with a paramset) may serve as a workaround, and hence this is low priority.
 ===== transition filter ===== ===== transition filter =====
- 
-TODO: move to tech:modelgen 
  
 The LRM description for the transition function is unclear. The situation where The LRM description for the transition function is unclear. The situation where
gnucap/manual/tech/modelgen-verilog.txt · Last modified: 2025/05/19 06:30 by felixs
 
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